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Datasheet File OCR Text:

LIS331DLM
MEMS digital output motion sensor ultra low-power high performance 3-axes "nano" accelerometer
Features

Wide supply voltage, 2.16 V to 3.6 V Low voltage compatible IOs, 1.8 V Ultra low-power mode consumption down to 10 A 2g/4g/8g dynamically selectable full-scale I2C/SPI digital output interface 8 bit resolution 2 independent programmable interrupt generators for free-fall and motion detection Sleep to wake-up function 6D orientation detection Embedded self-test 10000 g high shock survivability ECOPACK(R) RoHS and "Green" compliant (see Section 8)
LGA 16 (3x3x1 mm)
Description
The LIS331DLM is an ultra low-power high performance three axes linear accelerometer belonging to the "nano" family, with digital I2C/SPI serial interface standard output. The device features ultra low-power operational modes that allow advanced power saving and smart sleep to wake-up functions. The LIS331DLM has dynamically user selectable full scales of 2g/4g/8g and it is capable of measuring accelerations with output data rates from 0.5 Hz to 400 Hz. The self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate interrupt signal by inertial wake-up/free-fall events as well as by the position of the device itself. Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS331DLM is available in small thin plastic Land Grid Array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 C to +85 C. .
Applications

Motion activated functions Free-fall detection Intelligent power saving for handheld devices Pedometer Display orientation Gaming and virtual reality input devices Impact recognition and logging Vibration monitoring and compensation
Table 1.
Device summary
Temperature range [ C] -40 to +85 -40 to +85 Package LGA 16 LGA 16 Packaging Tray Tape and reel
Order code LIS331DLM LIS331DLMTR
July 2009
Doc ID 15102 Rev 4
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www.st.com 38
Contents
LIS331DLM
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 2.3.2 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 2.5.2 2.5.3 2.5.4 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sleep to wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 3.2 3.3 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 5.2 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.1 5.2.2 5.2.3 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Contents
6 7
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CTRL_REG3 [Interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 27 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CTRL_REG5 (24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h) 28 HP_FILTER_RESET (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 REFERENCE (26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h) 28 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OUT_X (29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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List of tables
LIS331DLM
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mechanical characteristics @ Vdd = 2.5 V, T = 25 C unless otherwise noted . . . . . . . . . . 7 Electrical characteristics @ Vdd = 2.5 V, T = 25 C unless otherwise noted . . . . . . . . . . . . 8 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 17 Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 24 Normal-mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 24 CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 High-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data signal on INT 1 and INT 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 REFERENCE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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LIS331DLM Table 49. Table 50. Table 51. Table 52. Table 53. Table 54.
List of tables INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of figures
LIS331DLM
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LIS331DLM electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 LGA16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Block diagram and pin description
1
1.1
Block diagram and pin description
Block diagram
Figure 1. Block diagram
X+ Y+ Z+
CHARGE AMPLIFIER
MUX A/D CONVERTER I2C CONTROL LOGIC SPI
CS SCL/SPC SDA/SDO/SDI SDO/SA0
a
ZYX-
SELF TEST
REFERENCE
TRIMMING CIRCUITS
CONTROL LOGIC CLOCK
&
INT 1 INT 2
INTERRUPT GEN.
1.2
Pin description
Figure 2. Pin connection
Z
Pin 1 indicator
X
1
13
1
9 Y (TOP VIEW) (BOTTOM VIEW)
5
DIRECTION OF THE DETECTABLE ACCELERATIONS
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Block diagram and pin description Table 2.
Pin# 1 2 3 4 5 6
LIS331DLM
Pin description
Name Vdd_IO NC NC SCL SPC GND SDA SDI SDO SDO SA0 CS INT 2 Reserved INT 1 GND GND Vdd Reserved GND Power supply for I/O pins Not connected Not connected I2C serial clock (SCL) SPI serial port clock (SPC) 0 V supply I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) SPI serial data output (SDO) I2C less significant bit of the device address (SA0) SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) Inertial interrupt 2 Connect to GND Inertial interrupt 1 0 V supply 0 V supply Power supply Connect to Vdd 0 V supply Function
7 8 9 10 11 12 13 14 15 16
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Mechanical and electrical specifications
2
2.1
Table 3.
Symbol
Mechanical and electrical specifications
Mechanical characteristics
Mechanical characteristics @ Vdd = 2.5 V, T = 25 C unless otherwise noted (1)
Parameter Test conditions FS bit set to 00 FS Measurement range(3) FS bit set to 01 FS bit set to 11 FS bit set to 00 8 bit representation So Sensitivity FS bit set to 01 8 bit representation FS bit set to 11 8 bit representation Dres TCSo TyOff TCOff Device resolution Sensitivity change vs temperature Typical zero-g level offset accuracy(4),(5) Zero-g level change vs temperature FS bit set to 00 ODR = 50 Hz FS bit set to 00 FS bit set to 00 Max delta from 25 C FS bit set to 00 X axis Vst Self-test output change(6),(7),(8) FS bit set to 00 Y axis FS bit set to 00 Z axis Top Wh Operating temperature range Product weight 3 -3 3 -40 20 Min. Typ.(2) 2.0 4.0 8.0 64 32 16 16 0.01 40 0.5 17 -17 17 32 -32 32 +85 mg %/C mg mg/C LSb LSb LSb C mgram LSB/g g Max. Unit
1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V. 2. Typical specifications are not guaranteed 3. Verified by wafer level test and measurement of initial offset and sensitivity 4. Typical zero-g level offset value after MSL3 preconditioning 5. Offset can be eliminated by enabling the built-in high pass filter 6. The sign of "Self-test output change" is defined by CTRL_REG4 STsign bit (Table 28), for all axes. 7. Self-test output changes with the power supply. "Self-test output change" is defined as OUTPUT[LSb](CTRL_REG4 ST bit=1) - OUTPUT[LSb](CTRL_REG4 ST bit=0). 1LSb=4g/256 at 8 bit representation, 2 g full-scale 8. Output data reach 99% of final value after 1/ODR+1 ms when enabling self-test mode, due to device filtering
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Mechanical and electrical specifications
LIS331DLM
2.2
Table 4.
Symbol Vdd Vdd_IO Idd IddLP IddPdn VIH VIL VOH VOL
Electrical characteristics
Electrical characteristics @ Vdd = 2.5 V, T = 25 C unless otherwise noted (1)
Parameter Supply voltage I/O pins supply voltage Current consumption in normal mode Current consumption in low-power mode Current consumption in power-down mode Digital high level input voltage Digital low level input voltage High level output voltage Low level output voltage DR bit set to 00 50 100 400 0.5 1 2 5 10 ODR/2 ODR = 100 Hz -40 1/ODR+1ms +85 Hz s Hz Hz Output data rate in normal mode 0.9*Vdd_IO 0.1*Vdd_IO 0.8*Vdd_IO 0.2*Vdd_IO
(3)
Test conditions
Min. 2.16 1.71
Typ.(2) 2.5
Max. 3.6 Vdd+0.1
Unit V V A A A V V V V
250 10 1
ODR
DR bit set to 01 DR bit set to 10 PM bit set to 010 PM bit set to 011
ODRLP
Output data rate in low-power mode
PM bit set to 100 PM bit set to 101 PM bit set to 110
BW Ton Top
System bandwidth Turn-on time(5)
(4)
Operating temperature range
C
1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V. 2. Typical specification are not guaranteed 3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. 4. Refer to Table 20 for filter cut-off frequency 5. Time to obtain valid data after exiting power-down mode
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Mechanical and electrical specifications
2.3
2.3.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5.
SPI slave timing values
Value (1) Parameter Min. Max. ns 10 6 8 5 15 50 9 50 ns MHz SPI clock cycle SPI clock frequency CS setup time CS hold time SDI input setup time SDI input hold time SDO valid output time SDO output hold time SDO output disable time 100 Unit
Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO)
Figure 3.
SPI slave timing diagram (2)
CS
(3)
(3)
tsu(CS)
tc(SPC)
th(CS)
(3)
SPC
(3)
tsu(SI)
th(SI)
MSB IN LSB IN (3)
SDI
(3)
tv(SO)
th(SO)
LSB OUT
tdis(SO)
(3)
SDO
(3)
MSB OUT
1. Values are guaranteed at 10MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production 2. Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both Input and output port 3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors
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Mechanical and electrical specifications
LIS331DLM
2.3.2
I2C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
Table 6.
Symbol f(SCL) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA)
I2C slave timing values
I2C standard mode (1) Parameter Min SCL clock frequency SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Bus free time between STOP and START condition 4 4.7 4 4.7 0 4.7 4.0 250 0.01 3.45 1000 300 Max 100 Min 0 1.3 s 0.6 100 0.01 20 + 0.1Cb (2) 20 + 0.1Cb (2) 0.6 0.6 s 0.6 1.3 0.9 300 ns 300 ns s Max 400 KHz I2C fast mode (1) Unit
tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(ST) tsu(SR) tsu(SP) tw(SP:SR)
1. Data based on standard I2C protocol requirement, not tested in production 2. Cb = total capacitance of one bus line, in pF
Figure 4.
I2C Slave timing diagram (a)
START tsu(SR) REPEATED START
SDA
tw(SP:SR)
START
tf(SDA)
tr(SDA)
tsu(SDA)
th(SDA) tsu(SP) STOP
SCL
th(ST)
tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
a. Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both port
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Mechanical and electrical specifications
2.4
Absolute maximum ratings
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7.
Symbol Vdd Vdd_IO Vin Supply voltage I/O pins supply voltage Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0) Acceleration (any axis, powered, Vdd = 2.5 V)
Absolute maximum ratings
Ratings Maximum value -0.3 to 6 -0.3 to 6 -0.3 to Vdd_IO +0.3 3000 g for 0.5 ms Unit V V V
APOW
10000 g for 0.1 ms 3000 g for 0.5 ms
AUNP TOP TSTG
Acceleration (any axis, unpowered) Operating temperature range Storage temperature range
10000 g for 0.1 ms -40 to +85 -40 to +125 4 (HBM) C C kV kV V
ESD
Electrostatic discharge protection
1.5 (CDM) 200 (MM)
Note:
Supply voltage on any pin should never exceed 6.0 V This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part This is an ESD sensitive device, improper handling can cause permanent damages to the part
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Mechanical and electrical specifications
LIS331DLM
2.5
2.5.1
Terminology
Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, 1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.
2.5.2
Zero-g level
Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2's complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see "Zero-g level change vs. temperature". The Zero-g level tolerance (TyOff) describes the standard deviation of the range of Zero-g levels of a population of sensors.
2.5.3
Self-test
Self-test allows to check the sensor functionality without moving it. The Self-test function is off when the self-test bit (ST) of CTRL_REG4 (control register 4) is programmed to `0`. When the self-test bit of CTRL_REG4 is programmed to `1` an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When self-test is activated, the device output level is given by the algebric sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
2.5.4
Sleep to wake-up
The "sleep to wake-up" function, in conjunction with low-power mode, allows to further reduce the system power consumption and develop new smart applications. LIS331DLM may be set in a low-power operating mode, characterized by lower date rates refreshments. In this way the device, even if sleeping, keep on sensing acceleration and generating interrupt requests. When the "sleep to wake-up" function is activated, LIS331DLM is able to automatically wake-up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. With this feature the system may be efficiently switched from low-power mode to fullperformance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility.
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Functionality
3
Functionality
The LIS331DLM is a "nano", low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I2C/SPI serial interface.
3.1
Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in the fF range.
3.2
IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user by an analog-to-digital converter. The acceleration data may be accessed through an I2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS331DLM features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. The LIS331DLM may also be configured to generate an inertial wake-up and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both free-fall and wake-up can be available simultaneously on two different pins.
3.3
Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff). The trimming values are stored inside the device in a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. This allows to use the device without further calibration.
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Application hints
LIS331DLM
4
Application hints
Figure 5. LIS331DLM electrical connection
Vdd
10F Vdd_IO
16
14
1
TOP VIEW
13
100nF
INT 1
5 6 8
9
INT 2
SDA/SDI/SDO
SCL/SPC
SDO/SA0
GND
Digital signal from/to signal controller.Signal's levels are defined by proper selection of Vdd_IO
The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 F Aluminum) should be placed as near as possible to the pin 14 of the device (common design practice). All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off. The functionality of the device and the measured acceleration data is selectable and accessible through the I2C or SPI interfaces.When using the I2C, CS must be tied high. The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user through the I2C/SPI interface.
4.1
Soldering information
The LGA package is compliant with the ECOPACK(R), RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C. Leave "pin 1 indicator" unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com.
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CS
LIS331DLM
Digital interfaces
5
Digital interfaces
The registers embedded inside the LIS331DLM may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be tied high (i.e. connected to Vdd_IO). Table 8. Serial interface pin description
Pin description SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C serial clock (SCL) SPI serial port clock (SPC) I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) I2C less significant bit of the device address (SA0) SPI serial data output (SDO)
Pin name CS SCL SPC SDA SDI SDO SA0 SDO
5.1
I2C serial interface
The LIS331DLM I2C is a bus slave. The I2C is employed to write data into registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 9.
Term Transmitter Receiver Master Slave
Serial interface pin description
Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS331DLM. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the normal mode.
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Digital interfaces
LIS331DLM
5.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The slave address (SAD) associated to the LIS331DLM is 000100xb. SDO/SA0 pad can be used to modify less significant bit of the device address. If SA0 pad is connected to voltage supply, LSb is `1' (address 0001001b) else if SA0 pad is connected to ground, LSb value is `0' (address 0001000b). This solution permits to connect and address two different accelerometers to the same I2C lines. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded inside the LIS331DLM behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address (SUB) is transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is `1', the SUB (register address) is automatically incremented to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit was `1' (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is `0' (Write) the Master will transmit to the slave with direction unchanged. Table explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 10. SAD+Read/Write patterns
SAD[6:1] 000100 000100 000100 000100 SAD[0] = SA0 0 0 1 1 R/W 1 0 1 0 SAD+R/W 00010001 (11h) 00010000 (10h) 00010011 (13h) 00010010 (12h)
Command Read Write Read Write
Table 11.
Master Slave
Transfer when master is writing one byte to slave
ST SAD + W SAK SUB SAK DATA SAK SP
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Digital interfaces
Table 12.
Master Slave
Transfer when master is writing multiple bytes to slave:
ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP
Table 13.
Master Slave ST
Transfer when master is receiving (reading) one byte of data from slave:
SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP
Table 14.
Master Slave
Transfer when Master is receiving (reading) multiple bytes of data from slave
ST SAD+W SAK SUB SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn't acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to be read. In the presented communication format MAK is Master Acknowledge and NMAK is no Master acknowledge.
5.2
SPI bus interface
The LIS331DLM SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
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Digital interfaces Figure 6.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
LIS331DLM Read and write protocol
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the Read register and Write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address is auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is `0' the address used to read/write data remains the same for every block. When MS bit is `1' the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged.
5.2.1
SPI read
Figure 7. SPI read protocol
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
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Digital interfaces The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 8.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
Multiple bytes SPI read protocol (2 bytes example)
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8
5.2.2
SPI write
Figure 9.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SPI write protocol
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing.
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Digital interfaces Figure 10. Multiple bytes SPI write protocol (2 bytes example)
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
LIS331DLM
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
5.2.3
SPI read in 3-wires mode
3-wires mode is entered by setting to `1' bit SIM (SPI serial interface mode selection) in CTRL_REG4. Figure 11. SPI read protocol in 3-wires mode
CS SPC SDI/O
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). Multiple read command is also available in 3-wires mode.
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Register mapping
6
Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 15. Register address map
Register address Name Reserved (do not modify) WHO_AM_I Reserved (do not modify) CTRL_REG1 CTRL_REG2 CTRL_REG3 CTRL_REG4 CTRL_REG5 HP_FILTER_RESET REFERENCE STATUS_REG -OUT_X -OUT_Y -OUT_Z Reserved (do not modify) INT1_CFG INT1_SOURCE INT1_THS INT1_DURATION INT2_CFG INT2_SOURCE INT2_THS INT2_DURATION Reserved (do not modify) rw r rw rw rw r rw rw rw rw rw rw rw r rw r r r r r r r r Type Hex 00 - 0E 0F 10 - 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E - 2F 30 31 32 33 34 35 36 37 38 - 3F 011 0000 00000000 011 0001 00000000 011 0010 00000000 011 0011 00000000 011 0100 00000000 011 0101 00000000 011 0110 00000000 011 0111 00000000 Reserved 010 0000 00000111 010 0001 00000000 010 0010 00000000 010 0011 00000000 010 0100 00000000 010 0101 010 0110 00000000 010 0111 00000000 010 1000 00000000 Not used 010 1001 output Dummy register Binary Reserved 000 1111 00010010 Dummy register Reserved Default Comment
010 1010 00000000 Not used 010 1011 output
010 1100 00000000 Not used 010 1101 output Reserved
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Register mapping
LIS331DLM
Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up.
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Register description
7
Register description
The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface.
7.1
WHO_AM_I (0Fh)
Table 16.
0
WHO_AM_I register
0 0 1 0 0 1 0
Device identification register. This register contains the device identifier that for LIS331DLM is set to 12h.
7.2
CTRL_REG1 (20h)
Table 17.
PM2
CTRL_REG1 register
PM1 PM0 DR1 DR0 Zen Yen Xen
Table 18.
PM2 - PM0 DR1, DR0 Zen Yen Xen
CTRL_REG1 description
Power mode selection. Default value: 000 (000: Power-down; Others: refer to Table 19) Data rate selection. Default value: 00 (00:50 Hz; Others: refer to Table 20) Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled) Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled)
PM bits allow to select between power-down and two operating active modes. The device is in power-down mode when PD bits are set to "000" (default value after boot). Table 19 shows all the possible power mode configurations and respective output data rates. Output data in the low-power modes are computed with low-pass filter cut-off frequency defined by DR1, DR0 bits. DR bits, in the normal-mode operation, select the data rate at which acceleration samples are produced. In low-power mode they define the output data resolution. Table 20 shows all the possible configuration for DR1 and DR0 bits.
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Register description
LIS331DLM
Table 19.
PM2 0 0 0 0 1 1 1
Power mode and low-power output data rate configurations
PM1 0 0 1 1 0 0 1 PM0 0 1 0 1 0 1 0 Power mode selection Power-down Normal mode Low-power Low-power Low-power Low-power Low-power Output data rate [Hz] ODRLP ODR 0.5 1 2 5 10
Table 20.
DR1(1) 0 0 1
1.
Normal-mode output data rate configurations and low-pass cut-off frequencies
DR0(1) 0 1 0 Output data rate [Hz] ODR 50 100 400 Low-pass filter cut-off frequency [Hz] 37 74 292
"11" bit configuration is not allowed and may cause incorrect device functionality.
7.3
CTRL_REG2 (21h)
Table 21.
BOOT
CTRL_REG2 register
HPM1 HPM0 FDS HPen2 HPen1 HPCF1 HPCF0
Table 22.
BOOT
CTRL_REG2 description
Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) High pass filter mode selection. Default value: 00
HPM1, HPM0
(00: normal mode; Others: refer to Table 23)
Filtered data selection. Default value: 0
FDS HPen2
(0: internal filter bypassed; 1: data from internal filter sent to output register)
High pass filter enabled for Interrupt 2 source. Default value: 0 (0: filter bypassed; 1: filter enabled)
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LIS331DLM Table 22.
HPen1 HPCF1, HPCF0
Register description CTRL_REG2 description (continued)
High pass filter enabled for Interrupt 1 source. Default value: 0 (0: filter bypassed; 1: filter enabled) High pass filter cut-off frequency configuration. Default value: 00 (00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64)
BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to `1' the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to `0'. Table 23.
HPM1 0 0 1
High-pass filter mode configuration
HPM0 0 1 0 High-pass filter mode Normal mode (reset reading HP_RESET_FILTER) Reference signal for filtering Normal mode (reset reading HP_RESET_FILTER)
HPCF[1:0]. These bits are used to configure high-pass filter cut-off frequency ft which is given by:
fs 1f t = ln 1 - ----------- ----- HPc 2
The equation can be semplified to the following approximated equation:
fs f t = --------------------6 HPc
Table 24.
High-pass filter cut-off frequency configuration
ft [Hz] Data rate = 50 Hz 1 0.5 0.25 0.125 ft [Hz] Data rate = 100 Hz 2 1 0.5 0.25 ft [Hz] Data rate = 400 Hz 8 4 2 1
HPcoeff2,1 00 01 10 11
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Register description
LIS331DLM
7.4
CTRL_REG3 [Interrupt CTRL register] (22h)
Table 25.
IHL
CTRL_REG3 register
PP_OD LIR2 I2_CFG1 I2_CFG0 LIR1 I1_CFG1 I1_CFG0
Table 26.
IHL PP_OD
CTRL_REG3 description
Interrupt active high, low. Default value: 0 (0: active high; 1: active low) Push-pull/Open drain selection on interrupt pad. Default value 0. (0: push-pull; 1: open drain) Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by reading INT2_SRC itself. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) Data signal on INT 2 pad control bits. Default value: 00. (see table below) Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by reading INT1_SRC register. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) Data signal on INT 1 pad control bits. Default value: 00. (see table below)
LIR2 I2_CFG1, I2_CFG0 LIR1 I1_CFG1, I1_CFG0
Table 27.
Data signal on INT 1 and INT 2 pad
I1(2)_CFG0 0 1 0 1 INT 1(2) Pad Interrupt 1 (2) source Interrupt 1 source OR interrupt 2 source Data ready Boot running
I1(2)_CFG1 0 0 1 1
7.5
CTRL_REG4 (23h)
Table 28.
0
CTRL_REG4 register
0 FS1 FS0 STsign 0 ST SIM
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Register description
Table 29.
FS1, FS0 STsign ST SIM
CTRL_REG4 description
Full-scale selection. Default value: 00. (00: 2 g; 01: 4 g; 11: 8 g) Self-test sign. Default value: 00. (0: self-test plus; 1 self-test minus) Self-test enable. Default value: 0. (0: self-test disabled; 1: self-test enabled) SPI serial interface mode selection. Default value: 0. (0: 4-wire interface; 1: 3-wire interface)
7.6
CTRL_REG5 (24h)
Table 30.
0
CTRL_REG5 register
0 0 0 0 0 TurnOn1 TurnOn0
Table 31.
TurnOn1, TurnOn0
CTRL_REG5 description
Turn-on mode selection for sleep to wake function. Default value: 00.
TurnOn bits are used for turning on the sleep to wake function.
7.7
HP_FILTER_RESET (25h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g. This allows to overcome the settling time of the high pass filter.
7.8
REFERENCE (26h)
Table 32.
Ref7
REFERENCE register
Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0
Table 33.
Ref7 - Ref0
REFERENCE description
Reference value for high-pass filter. Default value: 00h.
This register sets the acceleration value taken as a reference for the high-pass filter output. When filter is turned on (at least one of FDS, HPen2, or HPen1 bit is equal to `1') and HPM bits are set to "01", filter out is generated taking this value as a reference.
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Register description
LIS331DLM
7.9
STATUS_REG (27h)
Table 34.
ZYXOR
STATUS_REG register
ZOR YOR XOR ZYXDA ZDA YDA XDA
Table 35.
ZYXOR
STATUS_REG description
X, Y and Z axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data has overwritten the previous one before it was read) Z axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one) Y axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one) X axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one) X, Y and Z axis new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) Z axis new data available. Default value: 0 (0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available) Y axis new data available. Default value: 0 (0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available) X axis new data available. Default value: 0 (0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)
ZOR
YOR
XOR ZYXDA ZDA
YDA
XDA
7.10
OUT_X (29)
X-axis acceleration data. The value is expressed as two's complement with 8 bit data representation right justified.
7.11
OUT_Y (2Bh)
Y-axis acceleration data. The value is expressed as two's complement with 8 bit data representation right justified.
7.12
OUT_Z (2Dh)
Z-axis acceleration data. The value is expressed as two's complement with 8 bit data representation right justified.
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Register description
7.13
INT1_CFG (30h)
Table 36.
AOI
INT1_CFG register
6D ZHIE ZLIE YHIE YLIE XHIE XLIE
Table 37.
AOI 6D
INT1_CFG description
AND/OR combination of Interrupt events. Default value: 0. (See Table 38) 6 direction detection function enable. Default value: 0. (See Table 38) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Configuration register for interrupt 1 source. Table 38.
AOI 0 0 1 1
Interrupt 1 source configurations
6D 0 1 0 1 Interrupt mode OR combination of interrupt events 6 direction movement recognition AND combination of interrupt events 6 direction position recognition
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Register description
LIS331DLM
7.14
INT1_SRC (31h)
Table 39.
0
INT1_SRC register
IA ZH ZL YH YL XH XL
Table 40.
IA ZH ZL YH YL XH XL
INT1_SRC description
Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value: 0 (0: no interrupt, 1: Z High event has occurred) Z low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) Y high. Default value: 0 (0: no interrupt, 1: Y High event has occurred) Y low. Default value: 0 (0: no interrupt, 1: Y Low event has occurred) X high. Default value: 0 (0: no interrupt, 1: X High event has occurred) X low. Default value: 0 (0: no interrupt, 1: X Low event has occurred)
Interrupt 1 source register. Read only register. Reading at this address clears INT1_SRC IA bit (and the interrupt signal on INT 1 pin) and allows the refreshment of data in the INT1_SRC register if the latched option was chosen.
7.15
INT1_THS (32h)
Table 41.
0
INT1_THS register
THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 42.
INT1_THS description
Interrupt 1 threshold. Default value: 000 0000
THS6 - THS0
7.16
INT1_DURATION (33h)
Table 43.
0
INT1_DURATION register
D6 D5 D4 D3 D2 D1 D0
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Register description
Table 44.
D6 - D0
INT2_DURATION description
Duration value. Default value: 000 0000
D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen.
7.17
INT2_CFG (34h)
Table 45.
AOI
INT2_CFG register
6D ZHIE ZLIE YHIE YLIE XHIE XLIE
Table 46.
AOI 6D
INT2_CFG description
AND/OR combination of Interrupt events. Default value: 0. (See table below) 6 direction detection function enable. Default value: 0. (See table below) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Configuration register for Interrupt 2 source. Table 47.
AOI 0 0
Interrupt mode configuration
6D 0 1 Interrupt mode OR combination of interrupt events 6 direction movement recognition
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Register description Table 47.
AOI 1 1
LIS331DLM Interrupt mode configuration (continued)
6D 0 1 Interrupt mode AND combination of interrupt events 6 direction position recognition
7.18
INT2_SRC (35h)
Table 48.
0
INT2_SRC register
IA ZH ZL YH YL XH XL
Table 49.
IA ZH ZL YH YL XH XL
INT2_SRC description
Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred) Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred) Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) X high. Default value: 0 (0: no interrupt, 1: X high event has occurred) X low. Default value: 0 (0: no interrupt, 1: X low event has occurred)
Interrupt 2 source register. Read only register. Reading at this address clears INT2_SRC IA bit (and the interrupt signal on INT 2 pin) and allows the refreshment of data in the INT2_SRC register if the latched option was chosen.
7.19
INT2_THS (36h)
Table 50.
0
INT2_THS register
THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 51.
INT2_THS description
Interrupt 1 threshold. Default value: 000 0000
THS6 - THS0
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Register description
7.20
INT2_DURATION (37h)
Table 52.
0
INT2_DURATION register
D6 D5 D4 D3 D2 D1 D0
Table 53.
D6 - D0
INT2_DURATION description
Duration value. Default value: 000 0000
D6 - D0 bits set the minimum duration of the interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen.
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Package information
LIS331DLM
8
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 12. LGA16: mechanical data and package dimensions
Dimensions Ref.
A1 A2 A3 D1 E1 L1 L2 N1 N2 M P1 P2 T1 T2 d k 0.290 0.190 0.040 2.850 2.850 0.785 0.200 3.000 3.000 1.000 2.000 0.500 1.000 0.100 0.875 1.275 0.350 0.250 0.150 0.050
mm Min. Typ. Max.
1.000
inch Min. Typ.
0.0309 0.0079 3.150 0.1122 0.1181 0.1240 3.150 0.1122 0.1181 0.1240 1.060 2.060 0.0394 0.0417 0.0787 0.0811 0.0197 0.0394 0.160 0.0016 0.0039 0.0063 0.0344 0.0502 0.410 0.0114 0.0138 0.0161 0.310 0.0075 0.0098 0.0122 0.0059 0.0020
Max.
0.0394
Outline and mechanical data
LGA16 (3x3x1.0mm) Land Grid Array Package
7983231
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LIS331DLM
Revision history
9
Revision history
Table 54.
Date 16-Oct-2008 03-Nov-2008 21-Nov-2008 10-Jul-2009
Document revision history
Revision 1 2 3 4 Initial release Table , 15, 16 have been updated Updated Table 4 on page 10 Updated: Table 4 on page 10, Table 6 on page 12, Table 7 on page 13, Table 28 on page 28, Table 29 on page 29 Minor text changes to improve readability Changes
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LIS331DLM
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